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High Performance Dual Ended PWM Controller
POWER MANAGEMENT Description
The SC4808B-2 is a dual-ended, high frequency, integrated PWM controller, optimized for isolated applications that require minimum space. It can be configured for current or voltage mode operation with required control circuitry where secondary side error amplifier is used. Some of the key features are high frequency operation of 1 MHz that allows the use of smaller components thus saving cost and valuable board space. An internal ramp on the Current Sense pin allows Internal Slope Compensation programmed by an external resistor. Other features include programmable frequency up to 1MHz, Pulse by Pulse current and Line Monitoring Input with Hysteresis to reduce stress on the power components. A unique oscillator is used to synchronize two SC4808B2's to work out of phase. This minimizes the input and output ripple thus reducing noise on the output line and reducing stress and size of input/output filter components. The dual outputs can be configured in Push-Pull, Half Bridge and Full Bridge format with programmable dead time between two outputs depending on the size of the timing components. The SC4808B-2 also features a turn on threshold of 4.4V and is available in MSOP-10 package.
SC4808B-2
Features
u u u u u u u u u u u u u
120A starting current Pulse by pulse current limit Programmable operation up to 1MHz Internal soft start Programmable line undervoltage lockout Over current shutdown Dual output drive stages on push-pull configuration Programmable internal slope compensation Programmable mode of operation (peak current mode or voltage mode) External frequency synchronization Bi-phase mode of operation -40 to 105 C operating temperature MSOP-10 Lead-free package. This product is fully WEEE and RoHS compliant Telecom equipment and power supplies Networking power supplies Industrial power supplies Push-pull converter Half bridge converter Full bridge converter Isolated VRM's
Applications
u u u u u u u
Typical Application Circuit
Vo Vin Gnd_Out
RSENSE
Gnd_In
OUTA OUTB CS VCC
SYNC
RC REF
SYNC
FB
LUVLO GND
SC4808
Revision: Dec. 9, 2009
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SC4808B-2
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Supply Voltage Supply Current SYNC, RC,CS, LUVLO, REF to GND FB to GND REF Current OUTA/OUTB to GND OUTA/OUTB Source Current (peak) OUTA/OUTB Sink Current (peak) Power Dissipation at TA = 25C Thermal Resistance Junction Temperature Storage Temperature Range Lead Temperature (Soldering) 10 Sec. ESD Rating (Human Body Model)
Symbol VCC ICC
Maximum -0.5 to18 20 -0.5 to 7
Units V mA V V mA V mA mA W C/W C C C kV
VFB IREF VOUTA/B Isource Isink PD JA TJ TSTG TLEAD VESD
-0.5 to (V REF+ 0.5) 10 -0.5 to 18 -250 250 1.105 113.1 -40 to 150 -65 to 150 +300 2
Electrical Characteristics
Unless specified: VCC = 12V; CL = 100pF; TA = -40C to 105C
Parameter PWM Maximum Duty Cycle Minimum Duty Cycle Current Sense Gain Maximum Input Signal CS to Output Delay Over Current Threshold Internal Slope Compensation Resistor FB to CS Offset Output OUT Low Level OUT High Level Rise Time Fall Time
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Test Conditions
Min
Typ
Max
Unit
Fosc = 50kHz, FB = 5V, Measured at OUTA or OUTB Fosc = 50kHz, FB = 1.5V, Measured at OUTA or OUTB
48
49
50 0
% %
3 475 525 100 .850 .950 25 1.30 1.50 1.70 1 575 mV ns V k V
0 11.0
.50 11.25 25 25
.70 12.00
V V ns ns
2
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SC4808B-2
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: VCC = 12V; CL = 100pF; TA = -40C to 105C
Parameter VCC Under Voltage Lockout Start Threshold Hysteresis Line Under Voltage Lockout Start Threshold Hysteresis Soft Start Internal Soft Start Ramp Soft Start Duration
Test Conditions
Min
Typ
Max
Unit
4.0 100
4.40 140
4.5 200
V mV
R23 = 14k, R33 = 10k (see page 11) R23 = 14k, R33 = 10k (see page 11)
-3%
VREF 5.6% of VREF
+3%
V mV
200 Rcs = 1k (See formula in the application information section on page 18) 12
s/V s
Soft Start Delay Oscillator Oscillator Frequency Oscillator Ramp RC pin to GND capacitance Oscillator Frequency Range Sync/CLOCK Clock SYNC Threshold Sync Frequency Range Bandgap Reference Voltage ReferenceCurrent Overall Startup Current Operating Supply Current VCC Zener Shunt Voltage VCC < start threshold FB = 0V, CS = 0V IDD = 10mA 16 2.970 50 R osc = 11k , Cosc = 200pF 450
140
s
500 VREF/2 +0.25 22
550
KHz V pF
1000
KHz
1.0 F osc*1.3
V KHz
3.125 5
3.280
V mA
150 7
A mA V
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SC4808B-2
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Part Number SC4808B-2MSTRT(1)(2) Package MSOP-10 Temp. Range (T A) -40C to 105C
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.
(MSOP-10)
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SC4808B-2
POWER MANAGEMENT Pin Descriptions
FB: The inverting input to the PWM comparator. Stray inductances and parasitic capacitance should be minimized by utilizing ground planes and correct layout guide lines (see page 19). REF: A 0.1F or 47nF low ESR capacitor is required and must be placed right at the pin. CS: Current sense input and internal slope compensation are both provided via the CS pin. The current sense input from a sense resistor is used for the peak current and overcurrent comparators. An internal 1 to 3 feed back voltage divider provides a 3X amplification of the CS signal. This is used for comparison to the external error amplifier signal. If an external resistor is connected from CS to the current sense resistor, the internal current source will provide a programmable slope compensation. The value of the resistor will determine the level of compensation. At higher compensation levels, voltage mode of operation can be achieved. RC: The oscillator programming pin. The oscillator should be referenced to a stable reference voltage for an accurate and stable frequency. Only two components are required to program the oscillator, a resistor (tied to Vref and RC), and a capacitor (tied to the RC and GND). The following formula can be used for a close approximation of the oscillator frequency.
FOSC _ A 1 ROSC CTOT x 0 .8 FOSC _ B 1 ROSC CTOT x 0 .9
LUVLO: Line undervoltage lockout pin. An external resistive divider will program the undervoltage lockout level. The external divider should be referenced to the quiet analog ground (see page 19). During the LUVLO, the driver outputs are disabled and the softstart is reset. This pin can also function as an Enable/Disable. SYNC: SYNC is a positive edge triggered input with a threshold set to 1.0V. In a single controller operation, SYNC could be grounded or connected to an external synchronization clock within the SYNC frequency range (see page 3). In the Bi-Phase operation mode SYNC pins could be connected to the Cosc (Timing Capacitors) of the other controller. This will force an out of phase operation (see page 12). GND: Device power and analog ground. Careful attention should be paid to the layout of the ground planes (see page 19). OUTA and OUTB: Out of phase gate drive stages. The driver's peak source and sink current drive capability of 100mA, enables the use of an external MOSFET driver or a NPN/PNP transistor buffer. The oscillator RC network programs the oscillator frequency, which is twice the OUTA/OUTB frequency. To insure that the outputs do not overlap, a dead time can be generated between the two outputs by sizing the oscillator timing capacitor (see page 11). VCC: The supply input for the device. Once VCC has exceeded the UVLO limit, the internal reference, oscillator, drivers and logic are powered up. A low ESR capacitance, should be used for decoupling right at the IC pin to minimize noise problems.
where:
CTOT = C OSC + C SC 4808 + CCircuit CSC 4808 22 pF
Where the frequency is in Hertz, resistance in ohms, and capacitance in farads. The recommended range of timing resistors is between 10 kohm and 200kohm and range of timing capacitors is between 100pF and 1000pF. Timing resistors less than 10 kohm should be avoided. Refer to layout guide lines on (page 19) to achieve best results.
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SC4808B-2
POWER MANAGEMENT Block Diagram
VCC CS
Slope Comp.
OVER CURRENT
Peak Current
OUTA Enable
S R Q
OSC
500mv
Q T S Q Q
Disable
REF
R
LUVLO
Bandgap UVLO SOFT START
R
OUTB SYNC
2R
LUVLO GND
LUVLO
FB
RC
SYNC
Marking Information
Top Mark AB2B yyww Bottom Mark xxxx xxxx
yyww = Datecode (Example: 9912) xxxx = Semtech Lot # (Example: E901 xxxx 01-1)
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SC4808B-2
POWER MANAGEMENT SC4808B-2 Typical Characteristics (SC4808B-2A)
100.0
Start up Iq, Vcc = 4V
1.69
FB to CS Offset
1.68 1.67 FB to CS offset (V)
95.0 90.0 Iq(uA) 85.0 80.0 75.0
1.66 1.65 1.64 1.63 1.62 1.61
70.0 -40 -25 -10 5 20 35 50 Ta (C) 65 80 95 110 125
1.60 -40 -25 -10 5 20 35 50 Ta (C) 65 80 95 110 125
Iq (start up) vs. Temperature
FB to CS Offset vs. Temperature
3.90 3.85
Operating Iq, Vcc = 5V Operating Iq, Vcc = 5.25V
1100 1000 Current Sense (mV) 900 800 700 600 500 400
Max Current Sense Signal Over Current Signal
3.80 Iq (mA) 3.75 3.70 3.65 3.60 -40 -25 -10 5 20 35 50 Ta (C) 65 80 95 110 125
-40
-25
-10
5
20
35 50 Ta (C)
65
80
95
110
125
Iq (operating) vs. Temperature
Current sense vs. Temperature
3.22
Reference, Vcc = 5V
4.500 4.450 4.400 4.350 4.300 4.250 4.200
-40 -25 -10 5 20 35 50 Ta (C) 65 80 95 110 125
Vcc UVLO (Rising) Vcc UVLO (Falling)
3.21 3.2 3.19 3.18 3.17 3.16
Vcc UVLO (V)
Reference (V)
-40
-25
-10
5
20
35 50 Ta (C)
65
80
95
110
125
Reference vs. Temperature
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Vcc UVLO vs. Temperature
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SC4808B-2
POWER MANAGEMENT SC4808B-2 Typical Characteristics (Cont.)
100
Vcc UVLO (Hysteresis)
1400 1200 1000 800 600 400 200 -25 -10 5 20 35 50 Ta (C) 65 80 95 110 125 -40
Oscillator Frequency 1MHz Oscillator Frequency 500kHz
98 Vcc UVLO Hysteresis (mV) 96 94 92 90 88 86 84 -40 Oscillator Frequency (kHz)
-25
-10
5
20
35 50 Ta (C)
65
80
95
110
125
Vcc UVLO Hysteresis vs. Temperature
Oscillator Frequency vs. Temperature
3.170
LUVLO (Rising)
664
Sync. Frequency @ Fosc = 500kHz
3.165 3.160 3.155 LUVLO (V) 3.150 3.145 3.140 3.135 3.130 3.125 3.120 -40 -25 -10 5 20 35 50 Ta (C) 65 80 95 110 125
Synchronization Frequency (kHz)
662 660 658 656 654 652 650 -40 -25 -10 5 20 35 50 Ta (C) 65 80 95 110 125
Line UVLO vs. Temperature
Synchronization Frequency vs. Temperature
140
LUVLO (Hysteresis)
49.5
Maximum Duty Cycle
135 130 125 120 115 110 105 100 -40 Maximum Duty Cycle (%) -25 -10 5 20 35 50 Ta (C) 65 80 95 110 125 LUVLO Hysteresis (mV)
49.5 49.5 49.4 49.4 49.4 49.4 49.4 -40 -25 -10 5 20 35 50 Ta (C) 65 80 95 110 125
Line UVLO Hysteresis vs. Temperature
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Maximum Duty Cycle vs. Temperature
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SC4808B-2
POWER MANAGEMENT SC4808B-2 Typical Characteristics (Cont.)
180
Soft Start Delay Time
170 Soft Start Delay Time (us) 160 150 140 130 120 110 100 90 80 -40 -25 -10 5 20 35 50 Ta (C) 65 80 95 110 125
Soft Start Delay time vs. Temperature
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SC4808B-2
POWER MANAGEMENT Application Information
THEORY OF OPERATION The SC4808B-2 is a versatile double ended, high speed, low power, pulse width modulator that is optimized for applications requiring minimum space. The device contains all of the control and drive circuity required for isolated or non isolated power supplies where an external error amplifier is used. A fixed oscillator frequency (up to 1MHz) can be programmed by an external RC network. The SC4808B-2 is a peak current or voltage mode controller, depending on the amount of slope compensation, programmable with only one external resistor. The cycle by cycle peak current limit prevents core saturation when a transformer is used for isolation while the overcurrent circuitry initiates the softstart cycle. The SC4808B-2 dual output drive stages are arranged in a push-pull configuration. Both outputs switch at half the oscillator frequency using a toggle flip flop. The dead time between the two outputs is programmable depending on the values of the timing capacitor and resistors, thus limiting each output stage duty cycle to less than 50%. The SC4808B-2 also provides flexibility with programmable LUVLO thresholds, with built-in hysteresis. SUPPLY A single supply, VCC is used to provide the bias for the internal reference, oscillator, drivers, and logic circuitry of SC4808B-2. To ensure proper operation during start up, VCC slew rate of less than 10V/mS is recommended. PWM CONTROLLER SC4808B-2 is a double ended PWM controller that can be used in voltage or current mode applications. The SC4808B-2 provides a 4.4V VCC UVLO, and a 3.125V reference. The oscillator frequency is programmed by a resistor and a capacitor network connected to an external reference provided by the SC4808B-2. The two outputs, OUTA and OUTB, are 180 degrees out of phase and run at half of the oscillator frequency. An external error amplifier will provide the error signal to the FB pin of the SC4808B-2. The current sense input and internal slope compensation are both provided via the CS pin. The current sense input from a sense resistor is used for the peak current and overcurrent comparators. An internal 1 to 3 feedback volt(c) 2009 Semtech Corp. 10
age divider provides a 3X amplification of the CS signal. This is used for comparison to the external error amplifier signal. If an external resistor is connected from CS to the current sense resistor, the internal current source will provide a programmable slope compensation. The value of the resistor will determine the level of compensation. At higher compensation levels, voltage mode of operation can be achieved. The error amplifier signal at the FB pin will be used in conjunction with the CS signal to achieve regulation. Two levels of undervoltage lockout are also available. The LUVLO (line under voltage lockout) pin via an external resistive divider will program the undervoltage lockout level. During the LUVLO, the driver outputs are disabled and the softstart is reset. Once VCC has exceeded the UVLO (VCC under voltage lockout) limit, the internal reference, oscillator, drivers and logic are powered up. SYNC is a positive edge triggered input with a threshold set to 1.0V. By connecting an external control signal to the SYNC pin, the internal oscillator frequency will be synchronized to the positive edge of the external control signal. In a single controller operation, SYNC should be grounded or connected to an external synchronization clock within the SYNC frequency range (see page 3). In the Bi-phase operation mode a very unique oscillator is utilized to allow two SC4808B-2 to be synchronized together and work out of phase. This feature is setup by simple connection of the SYNC input to the RC pin of the other part. The fastest oscillator automatically becomes the master, forcing the two PWMs to operate out of phase. This feature minimizes the input and output ripples, and reduces stress on the capacitors.
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SC4808B-2
POWER MANAGEMENT Application Information (Cont.)
VCC UNDER VOLTAGE LOCK OUT Depending on the application and the voltages available, the SC4808B-2 (UVLO = 4.4V) can be used to provide the VCC undervoltage lock out function to ensure the converters controlled start up. Before the VCC UVLO has been reached, the internal reference, oscillator, OUTA/OUTB drivers, and logic are disabled. LINE UNDER VOLTAGE LOCK OUT The SC4808B-2 also provides a line undervoltage (LUVLO = Vref) function. The LUVLO pin is programmed via an external resistor divider connected as shown below. The actual start-up voltage can be calculated by using the equation below: OSCILLATOR The oscillator frequency is set by connecting a RC network as shown below.
REF C26 2.2u,16V
VCC
R27 15k
U4
5 4 3 2 REF FB CS RC SYNC GND OUTB OUTA VCC LUVLO 6 7 8 9 10
R28 10
C31 200p
1
C33 0.1u,25V
SC4808 SYNC 56.2k 10k R33
VStartup = VREF
(R23 + R33 ) x
R33
Vin
R23
The oscillator has a ramp voltage of about Vref/2. The oscillator frequency is twice the frequency of the OUTA and OUTB gate drive controls.
R24 10k D15 C26 2.2u,16V R25 18 R26 2.2k R27 15k U4
5 4 3 REF FB CS RC SYNC GND OUTB OUTA VCC LUVLO 6 7 8 9 10
REF
VCC
R28 10
C29 82p C31 200p
2 1
C33 0.1u,25V
The oscillator capacitor C31 is charged by a current sourced from the Vref through R27. Once the RC pin reaches about Vref/2, the capacitor is discharged internally by the SC4808B-2. It should be noted that larger capacitor values will result in a longer dead time during the down slope of the ramp. The following equation can be used as an approximation of the oscillator frequency and the Dead time:
FOSC _ A 1 ROSC CTOT x 0 .8 FOSC _ B 1 ROSC CTOT x 0 .9
SC4808 SYNC 56.2k Vin R23 10k R33
where: REFERENCE A 3.125V(SC4808B-2) reference voltage is available that can be used to source a typical current of 5mA to the external circuitry. The Vref can be used to provide the oscillator RC network with a regulated bias.
CTOT = C OSC + C SC 4808 + CCircuit CSC 4808 22 pF
Tdeadtime
COSC x VREF x 0.5 3 10 -3
The recommended range of timing resistors is between 10 kohm and 200kohm, range of timing capacitors is between 100pF and 1000pF. Timing resistors less than 10 kohm should be avoided.
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SC4808B-2
POWER MANAGEMENT Application Information (Cont.)
SYNC/Bi-Phase operation In noise sensitive applications where synchronization of the oscillator frequency to a reference frequency is required, the SYNC pin can accept the external clock. By connecting an external control signal to the SYNC pin, the internal oscillator frequency will be synchronized to the positive edge of the external control signal. SYNC is a positive edge triggered input with a threshold set to 1.0V (SC4808B-2). In a single controller operation, SYNC should be grounded or connected to an external synchronization clock within the SYNC frequency range (see page 3). FEED BACK The error signal from the output of an external error amplifier such as SC431 or SC4431 is applied to the inverting input of the PWM comparator at the FB pin either directly or via an opto coupler for the isolated applications. For best stability, keep the FB trace length as short as possible.
Vref Vout R37 2.2k R34 FB
6 3
Vout C35 R32 C36 R35 R36 C37
4
C40 22pF
5 4 5 1
MOCD207 C38 0.1u C39 22n
SC4431
Vref
R38
2
REF
REF
Rosc1 5 4 3 2 Cosc1 1 REF FB CS RC
U1
GND OUTB OUTA VCC LUVLO 6 7 8 9 10
Rosc2 5 4 3 2 Cosc2 1 REF FB CS RC
U2
GND OUTB OUTA VCC LUVLO 6 7 8 9 10
The signal at the FB pin is then compared to the 3X amplified signal from the current sense/ slope compensation CS pin. Matched out of phase signals are generated to control the OUTA and OUTB gate drives of the two phases. A single ramp signal is used to generate the control signals for both phases, hence achieving a tightly matched per phase operation. Voltages below 1.5V at the FB pin, will produce a 0% duty cycle at the OUTA/OUTB gate drives. This offset is to provide enough head room for the opto coupler used in isolated applications. GATE DRIVERS OUTA and OUTB are out of phase bipolar gate drive output stages, that are supplied from VCC and provide a peak source/sink current of about 100mA. Both stages are capable of driving the logic input of external MOSFET drivers or a NPN/PNP transistor buffer. The output stages switch at half the oscillator frequency. When the voltage on the RC pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This "dead time" between the two outputs, along with a slower output rise and fall time, insures that the two outputs can not be on at the same time. The dead time is programmable and depends upon the timing capacitor.
SYNC
SYNC
SC4808
SC4808
In the Bi-phase operation mode a very unique oscillator is utilized to allow two SC4808B-2's to be synchronized together and work out of phase. This feature is set up by a simple connection of the SYNC input to the RC pin of the other part. The fastest oscillator automatically becomes the master, forcing the two PWMs to operate out of phase. This feature minimizes the input and output ripples, and reduces stress on the capacitors.
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SC4808B-2
POWER MANAGEMENT Application Information (Cont.)
It should be noted that if high speed/high current drivers such as the SC1301 are used, careful layout guide lines must be followed in order to minimize stray inductance, which might cause negative voltages at the output of the drivers. This negative voltage can be clamped to a reasonable level by placing a small Schottky diode directly at the output of the driver as shown below.
VCC EN SC1301A
3 5 U3
REF C26 2.2u,16V
VCC
C23 0.1u
1 4
Gate_B D_B
U4
5 4 3 2 1 REF FB CS RC SYNC GND OUTB OUTA VCC LUVLO 6 7 8
R28 10
2
VCC
9 10
EN SC1301A
C33 0.1u,25V C34 0.1u
1
3 5 U6
SC4808 SYNC 56.2k Vin R23 10k
4
Gate_A D_A
R33
2
OVER CURRENT Two levels of over current protection are provided by the SC4808B-2. The current information is sensed at the CS pin and compared to a peak current limit level of 525mV. If the 525mV limit is exceeded, the OUTA and OUTB pulse widths and duty cycle is reduced until the CS pin reaches a second threshold of 950mV. At that point, the OUTA and OUTB are disabled, and after a delay of 140s, the internal softstart sequence is started. After the softstart duration (see page 21 for calculation of softstart time), normal operation is achieved, unless the over current condition is still present.
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SC4808B-2
POWER MANAGEMENT Application Information (Cont.)
SLOPE COMPENSATION (Current or Voltage mode of operation) In applications where a current mode control is used for regulation, the peak inductor current information is used to produce the average output current. If a small perturbation due to changes in supply voltage or noise pick up is generated, instability may occur if the duty cycle is >50%. This phenomenon is graphically shown below. The inductor current and disturbed inductor current are shown for three different duty cycles conditions. The top wave form shows the applications where the duty cycle D is less than 50%. As shown, even if an error is introduced, after only a few cycles the error converges to zero. The second wave form shows the case where D = 50%. Under this condition, even though the error does not completely disappear, it stays constant and is not getting larger. This will be seen as jitter at the inductor voltage. The bottom wave form shows D>50%. As shown, a very small error results in a much larger error only after a few cycles. This will cause instability in the converter and the average output inductor current. The output load will not be able to be kept in regulation.
i I
L L
: Small Inductor current perturbation : Inductor current
Instability in current mode operation due to Duty cycle >50%
D<50%
I
L
i
L
Note: After afew cycles the perturbation disappears and stable operation returns.
Time
Error
D=50%
IL
i
L
iL
Note: After afew cycles the perturbation is still present, although this will cause jitter, but there is no instability.
Time
Error
D>50%
I
L
i
L
iL
Error
Time
Note: After afew cycles the perturbation becomes larger, and causes instability.
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SC4808B-2
POWER MANAGEMENT Application Information (Cont.)
The instability can be corrected by modification of the peak current information slope. One of the methods to alter the peak current information is to add a positive going ramp to the output of the current sensing circuitry. The SC4808B-2 achieves this by using an internal slope compensation circuit. The oscillator ramp is internally buffered and an internal 25kOhms resistor in conjunction with an external resistor at the CS pin will program the level of slope compensation. If the Rslope comp is increased, the internal ramp becomes the dominant signal and more voltage mode of operation is achieved. As it can be calculated from the second formula below, a 100% voltage mode operation can be achieved by choosing Rslope comp to be greater than 6.25K ohms. Also if a 100% current mode of operation is required, Rslope comp is reduced to zero and the contribution from the internal ramp is completely eliminated.
VRamp x
Current Transformer
%Slope _ Comp =
(Rslope _ Comp + Rsense ) (Rslope _ Comp + Rsense) + Rint ernal
VCS
N = 100
10k R D C 2.2u,16V Rsense RSlope Comp Rosc 15k REF
or
0.2 x (%slope_ Comp) Rexternal Rint ernal * 1 - (0 .2 x %slope_ Comp)
6 7
5 4 3
REF FB
25k
GND
CS
Cfilter 82p Cosc 200p
2 1
RC SYNC
SC4808 RSlope Comp value will determine the Mode of operation (Voltage or Current)
The Peak current information is sensed and the result is realistically summed to the buffered oscillator ramp, as shown above. The value of the external resistor Rslope comp will determine the percentage of the slope compensation. As the value for Rslope comp is reduced, the current information becomes more dominant and the mode of operation becomes more current mode. At the same time the slope of the current information is modified to provide the slope compensation.
Next page illustrates how the buffered oscillator ramp is used to modify the sensed inductor current. It should be noted that in order for the slope compensation to be effective, the current sensed signal slope should be at least 50% less steeper than the oscillator positive ramp slope. The slope will include the magnetizing current of the transformer and the inductor output current in isolated applications. In non-isolated applications, the slope will only include the inductor output current.
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SC4808B-2
POWER MANAGEMENT Application Information (Cont.)
i I I I
L
: Small Inductor current perturbation : Inductor current : Sensed Mosfet current
L
Slope Compensation generation from Buffered Oscillator Ramp
D>50%
Note: Below wave forms are not to scale.
Sense CS
: Summation of Isense and slope compensation, at the CS pin of the SC4808.
IL
I
Sense
Buffered Oscillator Ramp
I
CS
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SC4808B-2
POWER MANAGEMENT Application Information (Cont.)
Below the benefits from the slope compensation become apparent. The top wave form shows the stable operation before the perturbation. The second wave form shows the perturbation and the instability caused from it if no slope compensation is added to the current information. The last wave form shows the slope compensation and the effect of it. The increase in the slope of the current information results in an early termination of the inductor current, hence a reduction in the amount of error. As the cycle is repeated, the perturbation is reduced and finally eliminated.
iL I I I
: Small Inductor current perturbation : Inductor current : Sensed Mosfet current
L
Stable current mode operation with Slope Compensation
D>50%
Sense
CS
: Summation of Isense and slope compensation, at the CS pin of the SC4808.
Stable operation ( no perturbation)
Error Signal from Error amplifier
I
L
I
Sense
Note: After a few cycles the perturbation becomes larger, and causes instability.
Instable operation ( with perturbation)
Error Signal from Error amplifier
IL
I
i
L
Sense
Note: After a few cycles the perturbation disappears and stable operation returns.
Stable operation (Slope Compensation Added)
Error Signal from Error amplifier
I
CS
IL
i
L
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SC4808B-2
POWER MANAGEMENT Application Information (Cont.)
SOFT START During start up of the converter, the discharged output capacitor and the load current have large supply current requirements. To avoid this a soft start scheme is usually implemented where the duty cycle of the regulator is gradually increased from 0% until the soft start duration is elapsed. SC4808B-2 has an internal soft start circuit that limits the duty cycle for a duration approximated by the formula below. Also the soft start circuitry is activated if an over current condition occurs. After an over current condition, OUTA and OUTB are disabled and kept low for a duration of about 140s. After the delay, the OUTA and OUTB are enabled while the soft start limits the duty cycle. If the over current condition persists, the soft start cycle repeats indefinitely. Approximate internal soft start duration can be calculated as below: START UP SEQUENCE Initially during the power up, the SC4808B-2 is in under voltage lock out condition. As the Vcc supply exceeds the UVLO limit of the SC4808B-2, the internal reference, oscillator, and logic circuitry are powered up. The OUTA and OUTB drivers are not enabled until the line under voltage lock out limit is reached. At that point, once the FB pin is above 1.5V, soft start circuitry starts the output drivers, and gradually increases the duty cycle from 0%. The soft start duration is internally set (see formula in Soft Start section). As the output voltage starts to increase, the error signal from the error amplifier starts to decrease. If isolation is required, the error amplifier output can drive the LED of the opto isolator. The output of the opto is connected in a common emitter configuration with a pull-up resistor to a reference voltage connected to the FB pin of the SC4808B2. The voltage level at the FB pin provides the duty cycle necessary to achieve regulation. If an over current condition occurs, the outputs are disabled and after a soft start delay time of about 100s, the softstart sequence mentioned above is repeated.
T SoftStart
(Ramp
SoftStart
)x
R Internal R CS
VREF 2
_ SlopeComp _ to _ GND
+ 1

If longer soft start durations are required, the simple external circuit shown below can be implemented.
REF C26 2.2u,16V
VCC
REF R37 1k
6
R27 15k
U4
5 4 REF FB CS RC SYNC GND OUTB OUTA VCC LUVLO 6 7 8 9 10
R28 10
C40 NA
5
3
56.2K MOCD207 Csoft start C31 200p
2 1
C33 0.1u,25V
SC4808 SYNC 56.2k Vin R23 10k R33
Approximate soft start duration can be calculated as below:
TSoftStart CSoftStart x R37
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SC4808B-2
POWER MANAGEMENT Application Information (Cont.)
LAYOUT GUIDELINES Careful attention to layout requirements are necessary for successful implementation of the SC4808B-2 PWM controller. High current switching is present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, such as the input capacitor and FET ground. 2). In the loop formed by the Input Capacitor(s) (Cin), the FET must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically "cleaner" grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). The connection between FETs and the Transformer should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible. Fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC4808B-2 is best placed over a quiet ground plane area. Avoid pulse currents in the Cin FET loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the VCC supply capacitor(s). Under no circumstances should GND be returned to a ground inside the Cin, Q1, Q2 loop. Avoid making a star connection between the quiet GND planes that the SC4808B-2 will be connected to and the noisy high current GND planes connected to the FETs. 6) The feed back connection between the error amplifier and the FB pin should be kept as short as possible The GND connections should be connected to the quiet GND used for the SC4808B-2. 7) If an Opto isolator is used for isolation, quiet primary and secondary ground planes should be used. The same precautions should be followed for the primary GND plane as mentioned in item 5 mentioned above. For the secondary GND plane, the GND plane method mentioned in item 4 should be followed. 8) All the noise sensitive components such as LUVLO resistive divider, reference by pass capacitor, Vcc bypass capacitor, current sensing circuitry, feedback circuitry, and the oscillator resistor/capacitor network should be connected as close as possible to the SC4808B-2. The GND return should be connected to the quiet SC4808B-2 GND plane. 9) The connection from the OUTA and OUTB of the SC4808B-2 should be minimized to avoid any stray inductance. If the layout can not be optimized due to constraints, a small Schottky diode may be connected from the OUTA/ B pins to the ground directly at the IC. This will clamp excessive negative voltages at the IC. If drivers are used, the Schottky diodes should be connected directly at the IC from the output of the driver to the driver ground (See page 9). 10) If the SYNC function is not used, the SYNC pin should be grounded at the SC4808B-2 GND to avoid noise pick up.
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SC4808B-2
POWER MANAGEMENT Gain & Phase Margin
50
Gain
225
40
Gain Phase
Phase (deg) 180
135 30
90
20 Gain (dB)
45 Phase (deg)
10
0
0
-45
-90 -10 -135 -20
-180
-30 10
100
1000 Freq (Hz)
10000
-225 100000
Typical SC4808B-2 Push Pull Converter Gain/Phase plot at Vin = 36V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz
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SC4808B-2
POWER MANAGEMENT Gain & Phase Margin (Cont.)
50
Gain
225
40
Gain Phase
Phase (deg) 180
135 30
90
20 Gain (dB)
45 Phase (deg)
10
0
0
-45
-90 -10 -135 -20
-180
-30 10
100
1000 Freq (Hz)
10000
-225 100000
Typical SC4808B-2 Push Pull Converter Gain/Phase plot at Vin = 48V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz
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SC4808B-2
POWER MANAGEMENT Gain & Phase Margin (Cont.)
50
Gain
225
40
Gain Phase
Phase (deg) 180
135 30
90
20 Gain (dB)
45 Phase (deg)
10
0
0
-45
-90 -10 -135 -20
-180
-30 10
100
1000 Freq (Hz)
10000
-225 100000
Typical SC4808B-2 Push Pull Converter Gain/Phase plot at Vin = 72V, Vout = 3.3V, Iout = 10A, Fosc = 650kHz
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SC4808B-2
POWER MANAGEMENT Typical Step Load
Vout 500mV/Div
Iout 5A/Div
Cout = 6X22uF (132uF) Ceramic
100us/Div
Typical SC4808B-2 Push Pull Converter Step Load plot at Vin = 48V, Vout = 3.3V, Step = 37% to 75% Iout, Fosc = 650kHz
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SC4808B-2
POWER MANAGEMENT Evaluation Board Schematics
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SC4808B-2
POWER MANAGEMENT Evaluation Board Bill of Materials
SC4808 Push Pull 3.3V 50W non Synchronous SC4808EVB__non_sync Revision: 1.1 Bill Of Materials Item
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65
October 7,2002 Reference
13:35:18 Part
5output_half_brick 3input_half_brick 2.2n 0.1u 22u,6.3V 1u,100V .1u,16V 10u,16V 22nF 2.2u,16V 1u,16V 82p 0.1u,25V 10nF 22n NA 100pF 1nF 470pF .1uF 2.2uF 16V MBRB2535CTL 1N5819HW ZM4743A CMOSH-3 LS4448 short REF Vcc SYNC 0.9uH LQH43MN102K011 SUD19N20-90 FZT853 FMMT718 0 10 20k 250 TBD 0 2.2 56.2k 10k 15 1k 15k 10 2.2k 10k 37.4k 18.2k 11.5k 25.5k 100 16.2 56.2k PA0500 P8208T PE-68386 SC4808 SC1301A SC4431 MOCD207 CBRHD-02
Quantity
1 1 2 6 6 3 1 2 1 1 1 2 1 1 2 1 1 1 1 1 1 2 4 1 8 1 1 1 1 1 1 1 2 1 1 4 2 1 1 2 1 2 1 1 1 2 3 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1
Manufacturer #
Foot Print
CON\5OUTPUT_HALF_BRICK CON\3INPUT_HALF_BRICK SM/C_1206 SM/C_0805 SM/C_1210_GRM SM/C_2220 SM/C_0805 SM/C_1210_GRM SM/C_1206 SM/C_1206 SM/C_1210_GRM SM/C_0805 SM/C_1206 SM/C_0805 SM/C_0805 SM/C_0805 SM/C_0805 SM/C_0805 SM/C_0805 SM/C_0805 SM/C_0805 DIODE_D2PAK SOD123 SMB/DO214 SOD523 SM/DO213AC VIA\2P ED5052 ED5052 ED5052 PG0006 SDIP0302 DPAKFET SM/SOT223_BCEC SM/R_0805 SM/R_1206 SM/R_1206 SM/R_1210_MCR SM/R_0805 SM/R_1206 SM/R_0805 SM/R_1206 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_1206 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_0805 SM/R_1206 SM/R_0805 PA0500 P8208T PE-68386 MSOP10 SOT23_5PIN SOT23_5PIN SO-8 CBRHD-02
CON1 CON2 C3,C1 C2,C10,C17,C24,C26,C32 C4,C5,C6,C7,C8,C9 C11,C12,C13 C14 C15,C16 C18 C19 C20 C22,C21 C23 C25 C27,C33 C28 C29 C30 C31 C34 C35 D2,D1 D3,D5,D6,D16 D4 D7,D9,D10,D11,D12,D13, D14,D15 D8 JP1 J1 J2 J3 L1 L2 M1,M2 Q1 Q2 R1,R7,R15,R19 R5,R2 R3 R4 R6,R11 R8 R9,R10 R12 R13 R14 R16,R24 R17,R27,R30 R18 R26,R20 R21 R22 R23 R25 R28 R29 R31 R32 T1 T2 T3 U1 U2,U3 U4,U5 U6 U7
GRM32DR60J226KA01 GRM55DR72E105KW01 GRM32DR61C106KA01
GRM32RR71H105KA011
CMOSH-3 (Central Semiconductor)
LQH43MN102K01L SUD19N20-90
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SC4808B-2
POWER MANAGEMENT Evaluation Board Gerber Plots
Board Layout Assembly Top
Board Layout Assembly Bottom
Board Layout Top
Board Layout Bottom
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SC4808B-2
POWER MANAGEMENT Evaluation Board Gerber Plots
Board Layout INNER1
Board Layout INNER2
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SC4808B-2
POWER MANAGEMENT Outline Drawing - MSOP-10
e A N 2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 12 B E D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.000 .030 .007 .003 .114 .114 .043 .006 .037 .011 .009 .118 .122 .118 .122 .193 BSC .020 BSC .016 .024 .032 (.037) 10 0 8 .004 .003 .010 1.10 0.00 0.15 0.75 0.95 0.17 0.27 0.08 0.23 2.90 3.00 3.10 2.90 3.00 3.10 4.90 BSC 0.50 BSC 0.40 0.60 0.80 (.95) 10 0 8 0.10 0.08 0.25
D aaa C A2 SEATING PLANE C bxN bbb A1 C A-B D A GAGE PLANE 0.25 (L1) DETAIL SEE DETAIL SIDE VIEW
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
H c
L
01
A
A
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA.
Land Pattern - MSOP-10
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.161) .098 .020 .011 .063 .224 (4.10) 2.50 0.50 0.30 1.60 5.70
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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